VHDL语言编写自动售货机 用VHDL语言或Verilog语言编写简单自动售货机
\u7528VHDL\u8bed\u8a00\u7f16\u5199\u81ea\u52a8\u552e\u8d27\u673a\u7a0b\u5e8f\u81ea\u52a8\u552e\u8d27\u673aVHDL\u7a0b\u5e8f
\uff081\uff09\u81ea\u52a8\u552e\u8d27\u673aVHDL\u7a0b\u5e8f\u5982\u4e0b\uff1a
--\u6587\u4ef6\u540d\uff1apl_auto1.vhd\u3002
--\u529f\u80fd\uff1a\u8d27\u7269\u4fe1\u606f\u5b58\u50a8\uff0c\u8fdb\u7a0b\u63a7\u5236\uff0c\u786c\u5e01\u5904\u7406\uff0c\u4f59\u989d\u8ba1\u7b97\uff0c\u663e\u793a\u7b49\u529f\u80fd\u3002
--\u8bf4\u660e\uff1a\u663e\u793a\u7684\u94b1\u6570coin\u7684\u4ee55\u89d2\u4e3a\u5355\u4f4d\u3002
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_auto1 is
port ( clk:in std_logic; --\u7cfb\u7edf\u65f6\u949f
set,get,sel,finish: in std_logic; --\u8bbe\u5b9a\u3001\u4e70\u3001\u9009\u62e9\u3001\u5b8c\u6210\u4fe1\u53f7
coin0,coin1: in std_logic; --5\u89d2\u786c\u5e01\u30011\u5143\u786c\u5e01
price,quantity :in std_logic_vector(3 downto 0); --\u4ef7\u683c\u3001\u6570\u91cf\u6570\u636e
item0 , act:out std_logic_vector(3 downto 0); --\u663e\u793a\u3001\u5f00\u5173\u4fe1\u53f7
y0,y1 :out std_logic_vector(6 downto 0); --\u94b1\u6570\u3001\u5546\u54c1\u6570\u91cf\u663e\u793a\u6570\u636e
act10,act5 :out std_logic); --1\u5143\u786c\u5e01\u30015\u89d2\u786c\u5e01
end PL_auto1;
architecture behav of PL_auto1 is
type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0);
signal ram :ram_type; --\u5b9a\u4e49RAM
signal item: std_logic_vector(1 downto 0); --\u5546\u54c1\u79cd\u7c7b
signal coin: std_logic_vector(3 downto 0); --\u5e01\u6570\u8ba1\u6570\u5668
signal pri,qua:std_logic_vector(3 downto 0); --\u5546\u54c1\u5355\u4ef7\u3001\u6570\u91cf
signal clk1: std_logic; --\u63a7\u5236\u7cfb\u7edf\u7684\u65f6\u949f\u4fe1\u53f7
begin
com:process(set,clk1)
variable quan:std_logic_vector(3 downto 0);
begin
if set='1' then ram(conv_integer(item))<=price & quantity;act<="0000";
--\u628a\u5546\u54c1\u7684\u5355\u4ef7\u3001\u6570\u91cf\u7f6e\u5165\u5230RAM
elsif clk1'event and clk1='1' then act5<='0'; act10<='0';
if coin0='1' then
if coin<"1001"then coin<=coin+1; --\u6295\u51655\u89d2\u786c\u5e01\uff0ccoin\u81ea\u52a01
else coin<="0000";
end if;
elsif coin1='1' then
if coin<"1001"then coin<=coin+2; --\u6295\u51651\u5143\u786c\u5e01\uff0ccoin\u81ea\u52a02
else coin<="0000";
end if;
elsif sel='1' then item<=item+1; --\u5bf9\u5546\u54c1\u8fdb\u884c\u5faa\u73af\u9009\u62e9
elsif get='1' then --\u5bf9\u5546\u54c1\u8fdb\u884c\u8d2d\u4e70
if qua>"0000" and coin>=pri then coin<=coin-pri;quan:=quan-1;
ram(conv_integer(item))<=pri & quan;
if item="00" then act<="1000"; --\u8d2d\u4e70\u65f6\uff0c\u81ea\u52a8\u552e\u8d27\u673a\u5bf94\u79cd\u5546\u54c1\u7684\u64cd\u4f5c
elsif item="01" then act<="0100";
elsif item="10" then act<="0010";
elsif item="11" then act<="0001";
end if;
end if;
elsif finish='1' then --\u7ed3\u675f\u4ea4\u6613\uff0c\u9000\u5e01\uff08\u627e\u5e01\uff09
if coin>"0001" then act10<='1';coin<=coin-2; --\u6b64IF\u8bed\u53e5\u5b8c\u6210\u627e\u5e01\u64cd\u4f5c
elsif coin>"0000" then act5<='1'; coin<=coin-1;
else act5<='0'; act10<='0';
end if;
elsif get='0' then act<="0000";
for i in 4 to 7 loop
pri(i-4)<=ram (conv_integer(item))(i); --\u5546\u54c1\u5355\u4ef7\u7684\u8bfb\u53d6
end loop;
for i in 0 to 3 loop
quan(i):=ram(conv_integer(item))(i); --\u5546\u54c1\u6570\u91cf\u7684\u8bfb\u53d6
end loop;
end if;
end if;
qua<=quan;
end process com;
m32:process(clk) --\u6b64\u8fdb\u7a0b\u5b8c\u6210\u5bf932Mhz\u7684\u8109\u51b2\u5206\u9891
variable q: std_logic_vector( 24 downto 0);
begin
if clk'event and clk='1' then q:=q+1;
end if;
if q="111111111111111111111111" then clk1<='1';
else clk1<='0';
end if;
end process m32;
code0:process(item) --\u5546\u54c1\u6307\u793a\u706f\u8bd1\u7801
begin
case item is
when "00"=>item0<="0111";
when "01"=>item0<="1011";
when "10"=>item0<="1101";
when others=>item0<="1110";
end case;
end process;
code1: process (coin) --\u94b1\u6570\u7684BCD\u5230\u4e03\u6bb5\u7801\u7684\u8bd1\u7801
begin
case coin is
when "0000"=>y0<="0000001";
when "0001"=>y0<="1001111";
when "0010"=>y0<="0010010";
when "0011"=>y0<="0000110";
when "0100"=>y0<="1001100";
when "0101"=>y0<="0100100";
when "0110"=>y0<="0100000";
when "0111"=>y0<="0001111";
when "1000"=>y0<="0000000";
when "1001"=>y0<="0000100";
when others=>y0<="1111111";
end case;
end process;
code2: process (qua) --\u5355\u4ef7\u7684BCD\u5230\u4e03\u6bb5\u7801\u7684\u8bd1\u7801
begin
case qua is
when "0000"=>y1<="0000001";
when "0001"=>y1<="1001111";
when "0010"=>y1<="0010010";
when "0011"=>y1<="0000110";
when "0100"=>y1<="1001100";
when "0101"=>y1<="0100100";
when "0110"=>y1<="0100000";
when "0111"=>y1<="0001111";
when "1000"=>y1<="0000000";
when "1001"=>y1<="0000100";
when others=>y1<="1111111";
end case;
end process;
end behav;
\u7528verilog HDL \u6539\u6210VHDL \u5c31\u53ef\u4ee5\u4e86 \u7528\u72b6\u6001\u673a\u5199\u7684
/*\u4fe1\u53f7\u5b9a\u4e49\uff1a
clk\uff1a \u65f6\u949f\u8f93\u5165\uff1b
reset\uff1a \u4e3a\u7cfb\u7edf\u590d\u4f4d\u4fe1\u53f7\uff1b
half_dollar\uff1a \u4ee3\u8868\u6295\u51655\u89d2\u786c\u5e01\uff1b
one_dollar\uff1a \u4ee3\u8868\u6295\u51651\u5143\u786c\u5e01\uff1b
half_out\uff1a \u8868\u793a\u627e\u96f6\u4fe1\u53f7\uff1b
dispense\uff1a \u8868\u793a\u673a\u5668\u552e\u51fa\u4e00\u74f6\u996e\u6599\uff1b
collect\uff1a \u8be5\u4fe1\u53f7\u7528\u4e8e\u63d0\u793a\u6295\u5e01\u8005\u53d6\u8d70\u996e\u6599\u3002 */
module sell(one_dollar,half_dollar,
collect,half_out,dispense,reset,clk);
parameter idle=0,one=2,half=1,two=3,three=4;
//idle,one,half,two,three\u4e3a\u4e2d\u95f4\u72b6\u6001\u53d8\u91cf\uff0c\u4ee3\u8868\u6295\u5165\u5e01\u503c\u7684\u51e0\u79cd\u60c5\u51b5
input one_dollar,half_dollar,reset,clk;
output collect,half_out,dispense;
reg collect,half_out,dispense;
reg[2:0] D;
always @(posedge clk)
begin
if(reset)
begin
dispense=0; collect=0;
half_out=0; D=idle;
end
case(D)
idle:
if(half_dollar) D=half;
else if(one_dollar)
D=one;
half:
if(half_dollar) D=one;
else if(one_dollar)
D=two;
one:
if(half_dollar) D=two;
else if(one_dollar)
D=three;
two:
if(half_dollar) D=three;
else if(one_dollar)
begin
dispense=1; //\u552e\u51fa\u996e\u6599
collect=1; D=idle;
end
three:
if(half_dollar)
begin
dispense=1; //\u552e\u51fa\u996e\u6599
collect=1; D=idle;
end
else if(one_dollar)
begin
dispense=1; //\u552e\u51fa\u996e\u6599
collect=1;
half_out=1; D=idle;
end
endcase
end
endmodule
use ieee.std_logic_1164.all;
entity autosell is port(
A,B,C:in std_logic;--3种商品
in_money,out_money:in std_logic;--投币，和退币
out_m:out std_logic;--出币开关
Ya,Yb,Yc:out std_logic;--指示灯
ya_out,yb_out,yc_out:out std_logic);--出货信号
end;
architecture behaviol of autosell is
signal count:integer range 0 to 5;--技数
signal a1,b1,c1:std_logic;
begin
process(out_money,in_money,A,B,C)
begin
if in_money='1' then --投币
count<=count+1;
end if;
if count>0 then a1<='1';else a1<='0';end if;
if count>2 then b1<='1';else b1<='0';end if;
if count>4 then c1<='1';else c1<='0';end if;
Ya<=a1;Yb<=b1;Yc<=c1; --指示灯亮
if (a1<='1' and A='1') then --按键选择商品
ya_out<='1';count<=count-1;else ya_out<='0';
end if;
if (b1<='1' and B='1') then
yb_out<='1';count<=count-3;else yb_out<='0';
end if;
if (c1<='1' and C='1') then
yc_out<='1';count<=count-5; else yc_out<='0';
end if;
if out_money='1' then --退币
count<=0;out_m<='1';
else out_m<='0';
end if;
end process;
end;
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