verilog hdl 求助一个8位移位寄存器。。不知道怎么回事，总是没对 8位移位寄存器 verilog hdl

\u7528Verilog HDL\u7f16\u7a0b\u8bbe\u8ba18\u4f4d\u5de6\u53f3\u79fb\u79fb\u4f4d\u5bc4\u5b58\u5668\u7535\u8def\u3002

module Verilog1(clk,ldn,k,d,q);

input clk,ldn,k;
input [7:0] d;
output [7:0] q;

reg[7:0] d_reg,q_reg;
always@(negedge ldn)
if(!ldn)
d_reg <= d;

always@(posedge clk )
begin
if(k)
begin//right
q_reg[7:0] <= {1'b00,d_reg[7:1]};
end
else q_reg[7:0] <= {d_reg[6:0],1'b0};
end

assign q = q_reg;
endmodule

module yiweijicun(in,out,clk,rst); input [7:0] in; input clk,rst; output [7:0] out; reg [7:0] out; reg [7:0] temp; always @(posedge clk) begin if (!rst) out=0; else begin if(load) temp=in; else begin out=(out

integer i=0;
也就是i是32位的，你要做8位的，那么i=i+1;应该累加8次就把数据输出，这点没有体现，i是32位的那么不设限制的话也就是i会累加32次才回到初始

module yiweijicun(in,out,clk,rst);
input [7:0] in;
input clk,rst;
output [7:0] out;
reg [7:0] out;
reg [7:0] temp;

always @(posedge clk)

begin
if (!rst)
out=0;
else
begin if(load)
temp=in;
else begin
out=(out<<1);
out[0]=temp[7];
end
end
end
endmodule

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