verilog问题，， verilog 问题
verilog \u57fa\u672c\u95ee\u9898\u8981\u6c42\u662f\u8bf4\u5728\u65f6\u949f\u4e0b\u964d\u6cbf\u6e05\u96f6\uff0c\u800c\u4e0d\u662f\u68c0\u6d4b\u5230\u65f6\u949f\u4e0b\u964d\u6cbf\u6e05\u96f6\u3002
\u4e5f\u5c31\u662f\u8bf4\uff0c\u68c0\u6d4b\u5230\u65f6\u949f\u4e0b\u964d\u6cbf\u7684\u65f6\u5019\uff0c\u5982\u679cCLR\u6709\u6548\u5219\u6e05\u96f6\u3002
\u81f3\u4e8e\u8981or\u4e00\u4e2a\u6e05\u96f6\u7684\u4e0a\u5347\u6cbf\uff0c\u6211\u4e2a\u4eba\u7684\u7406\u89e3\u662f\u56e0\u4e3a\u8fd9\u4e2a\u6a21\u5757\u7684\u524d\u9762\u8fd8\u6709\u4e00\u4e2aD\u89e6\u53d1\u5668\uff0c\u524d\u9762\u90a3\u4e2aD\u89e6\u53d1\u5668\u7684\u7ed3\u679cQ\u4f5c\u4e3a\u8fd9\u4e2a\u6a21\u5757\u7684D\u8f93\u5165\u3002\u800c\u524d\u9762\u90a3\u4e2aD\u89e6\u53d1\u5668\u7684\u65f6\u949fCLK\u548c\u6e05\u96f6\u4fe1\u53f7CLR\u4e5f\u88ab\u5f15\u5230\u8fd9\u4e2a\u6a21\u5757\u4e2d\uff0c\u4f7f\u524d\u540e\u4e24\u79cdD\u89e6\u53d1\u5668\u540c\u6b65\u5de5\u4f5c\u3002\u5f53\u524d\u9762\u7684D\u89e6\u53d1\u5668CLR\u6709\u6548\u6e05\u96f6\u7684\u65f6\u5019\uff0c\u540e\u9762\u7684D\u89e6\u53d1\u5668\u4e5f\u5e94\u8be5\u8ddf\u968f\u524d\u9762\u7684\u6e05\u96f6\u3002
\u4f60\u662f\u4e0d\u662f\u9519\u8bef\u63d0\u793a\uff1aError (10200): Verilog HDL Conditional Statement error at \u2026\u2026: cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
\u8fd9\u662f\u56e0\u4e3a\uff0c\u4f60\u7684\u201calways@(posedge clk or negedge r_est)\u201d\u8868\u660e\u5728clk\u4e0a\u5347\u6cbf\u6216r_est\u4e0b\u964d\u6cbf\u8fd9\u4e24\u4e2a\u654f\u611f\u4e8b\u4ef6\u53d1\u751f\u65f6always\u8bed\u53e5\u5757\u5f97\u4ee5\u89e6\u53d1\uff1b\u800calways\u4e2d\u7684if\u6761\u4ef6\u8bed\u53e5\u5fc5\u987b\u81f3\u5c11\u6709\u4e00\u4e2a\u6761\u4ef6\u6307\u5411\u5176\u4e2d\u4e00\u4e2a\u654f\u611f\u4e8b\u4ef6\uff08\u8fb9\u754c\u6807\u8bc6\u7b26\uff09\uff1b\u6240\u4ee5\u5199\u6210\u201cif\uff08r_est)...else...\u201d\u5c31\u4f1a\u51fa\u9519\u3002
\u4f60\u53ef\u4ee5\u628a\u201calways@(posedge clk or negedge r_est)\u201d\u6539\u4e3a\u201calways@(posedge clk or posedge r_est)\u201d\u518d\u7f16\u8bd1\u8bd5\u8bd5\uff0c\u5e94\u8be5\u5c31\u6ca1\u95ee\u9898\u4e86\u3002
\u4f60\u53f3\u952e\u8be5\u9519\u8bef\u70b9\u51fb\u201cHelp\u201d\u91cc\u662f\u8fd9\u4e48\u8bf4\u7684\uff1a
CAUSE: In a conditional statement at the specified location in a Verilog Design File (.v), you specified a condition that Quartus II Integrated Synthesis cannot use to classify the edges in the enclosing always construct's event control. When an event control contains multiple edges, Quartus II Integrated Synthesis distinguishes the asynchronous control signals from the clock by analyzing the conditional statements in the always construct. For example, the following code fragment contains an always construct whose event control contains three edges---two asynchronous resets and a clock.
always @ (posedge clk or posedge rst1 or posedge rst2)
begin
if ( rst1 || rst2 )
q <= 1'b0;
else
q <= d;
end
Quartus II Integrated Synthesis uses the if condition to identify the two asynchronous resets and, by implication, the clock. For edge classification, Quartus II Integrated Synthesis requires that a condition fall into one of two categories. It can refer to a single edge identifier (to match posedge events) or its complement (to match negedge events), for example, rst1, !rst1, rst1 == 1'b1, rst1 == 1'b0. It can also OR two or more expressions that each refer to a single edge identifier or its complement, for example, (rst1 || rst2), (!rst1 || !rst2).
You can receive this error if your condition tests for the wrong polarity, or if it tests for the value of a variable that is not an edge in the event control. For example, to match a posedge rst event, the condition must be rst or rst = 1'b1.
Finally, you can receive this error if you are attempting to use a single condition expression to test for both an asynchronous reset/set and a synchronous reset/set condition. The following code fragment contains an example of an illegal condition expression:
always @ (posedge clk or posedge rst)
begin
if ( rst || sync_rst )
q <= 1'b0;
else
q <= d;
end
Quartus II Integrated Synthesis generates this error message when compiling this design because it cannot match sync_rst to an edge on the sensitivity list.
\u5176\u4e2d\u5173\u952e\u7684\u8bed\u53e5\u6211\u6458\u8bd1\u4e00\u4e0b\uff0c\u4e0d\u4e00\u5b9a\u8bd1\u5f97\u51c6\u786e\uff0c\u4e0d\u8fc7\u5927\u4f53\u610f\u601d\u6211\u60f3\u4f60\u5e94\u8be5\u53ef\u4ee5\u4e86\u89e3\u4e86\uff1a
\u539f\u56e0\uff1a\u2026\u2026\u6307\u5b9a\u4e86\u4e00\u4e2a\u6761\u4ef6\uff0cQuartus II \u7efc\u5408\u5668\u4e0d\u80fd\u591f\u5c06\u8be5\u6761\u4ef6\u7528\u4e8e\u5728\u5c01\u95ed\u7684always\u7ed3\u6784\u7684\u4e8b\u4ef6\u63a7\u5236\u4e2d\u5bf9\u8fb9\u754c\u8fdb\u884c\u533a\u5206\u3002\u5f53\u4e00\u4e2a\u4e8b\u4ef6\u63a7\u5236\u4e2d\u5305\u542b\u591a\u91cd\u8fb9\u754c\uff0cQuartus II \u7efc\u5408\u5668\u901a\u8fc7\u5206\u6790always\u7ed3\u6784\u4e2d\u7684\u6761\u4ef6\u8bed\u53e5\u6765\u5bf9\u65f6\u949f\u548c\u5f02\u6b65\u63a7\u5236\u4fe1\u53f7\u52a0\u4ee5\u533a\u5206\u3002\u2026\u2026
Quartus II \u7efc\u5408\u5668\u91c7\u7528if\u6761\u4ef6\u6765\u9274\u522b\u4e24\u4e2a\u5f02\u6b65reset\u4fe1\u53f7\uff0c\u5e76\u9690\u542b\u5730\u9274\u522b\u4e86clock\u4fe1\u53f7\u3002\u4e3a\u4e86\u5206\u7c7b\u7684\u9700\u8981\uff0cQuartus II \u7efc\u5408\u5668\u9700\u8981\u6709\u4e00\u4e2a\u6761\u4ef6\u843d\u5165\u4e24\u4e2a\u7c7b\u522b\u4e4b\u4e00\u3002\u5b83\u53ef\u4ee5\u6307\u5411\u4e00\u4e2a\u5355\u72ec\u7684\u8fb9\u754c\u6807\u8bc6\u7b26\uff08\u4ee5\u5339\u914dposedge\u4e8b\u4ef6\uff09\u6216\u5b83\u7684\u8865\u8bed\uff08\u4ee5\u5339\u914dnegedge\u4e8b\u4ef6\uff09\uff0c\u4f8b\u5982\uff0c rst1, !rst1, rst1 == 1'b1, rst1 == 1'b0\u3002\u5b83\u4e5f\u53ef\u4ee5\u662fOR\u4e24\u4e2a\u6216\u66f4\u591a\u7684\u8868\u8fbe\u5f0f\uff0c\u5176\u4e2d\u6bcf\u4e00\u4e2a\u6307\u5411\u4e00\u4e2a\u5355\u72ec\u7684\u8fb9\u754c\u6807\u8bc6\u7b26\u6216\u5b83\u7684\u8865\u8bed\u2026\u2026
\u5f53\u4f60\u7684\u6761\u4ef6\u6d4b\u8bd5\u53d1\u73b0\u9519\u8bef\u6781\u6027\uff0c\u6216\u8005\u5b83\u6d4b\u8bd5\u53d8\u91cf\u7684\u503c\uff0c\u4f46\u8be5\u503c\u5728\u4e8b\u4ef6\u63a7\u5236\u4e2d\u5e76\u4e0d\u662f\u4e00\u4e2a\u8fb9\u754c\u65f6\uff0c\u4f60\u4f1a\u63a5\u5230\u8fd9\u4e2a\u9519\u8bef\u3002\u4f8b\u5982\uff0c\u4e3a\u4e86\u5339\u914d\u4e00\u4e2aposedge rst\u4e8b\u4ef6\uff0c\u6761\u4ef6\u5fc5\u987b\u662frst\u6216rst = 1'b1\u3002
\u7f16\u8bd1\u9519\u8bef\u65f6\u591a\u770b\u770bHelp\uff0c\u8bb2\u5f97\u5f88\u8be6\u7ec6~
这里要注意，C是两位的二进制数，而S1和S2是一位的二进制数，&是按位的与运算。按位的与运算如果参与运算的数据位数不等时，会先将其补完整。而补充的规则应是左边加0。
因此，
Y=S1&C=2'b01&2'b10=2'b00;
Y=((~S2)&C);=~2'b00&2'b10=2'b11&2'b10=2'b10;
特别说明，正常情况下不同位长的数据参加按位逻辑运算应该是有问题的，照理，EDA工具至少应该会报出Warning信息，以提示该语句存在的问题。
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