求助英文翻译、汉译英
[\u6c49\u8bd1\u82f1]\u6c42\u82f1\u6587\u7ffb\u8bd1I certainly like the handsome dogs, but as a female audience, I clearly prefers film actor, he reminds me of when leonardo dicaprio young, of course not. "Titanic", but the jack "growing pains" of Luke, the handsome, pure and confusion of the boy.
The strategy of "going out" to the implementation of the rapid development of China's foreign trade, and enterprises to participate in the international competition strength, not only to promote their own the development of national economy, industry structure adjustment and reasonable allocation of factor of production has made the contribution to three industries so as to promote peace development, promote industrial internal upgrade.
Is English Field Programmable - FPGA Gate Array, namely the abbreviation of Field Programmable gates Array, it is in the GAL PAL and Programmable devices, CPLD etc. Based on the further development of the product. It is a special integrated circuits (ASIC) in the field of a half customization, and circuit solve the custom, and overcome the circuit of the original programmable gate device limited number of faults.The FPGA principle.
Using the Logic element Array FPGA Logic (LCA) such a concept Cell Array, including Configurable Logic module which CLB (Configurable Logic) and Output IOB Input module (which) and Output Input internal connection (Interconnect) three parts. The basic characteristics of the FPGA mainly are:
1) using the FPGA design ASIC circuit, users don't need cast piece, can get to share the chip.
2) can do other full customization FPGA or half of the pilot sample custom ASIC circuit.
3) the FPGA internal has abundant triggers and I/O foot.
4) the FPGA design cycle is an ASIC circuits, the lowest cost and risk of the smallest components.
5) CHMOS USES high-speed FPGA technology, low power consumption, and CMOS, TTL level.
Can say, the FPGA chip is small batch system to improve the reliability of system integration, is one of the best choice.
The FPGA are stored in RAM pieces by setting its work procedures to the state, therefore, when need to work within the RAM chips for programming. Users can according to different configuration model, using different programming.
When the power is in an EPROM chip, FPGA will read piece inside programming data, after the completion of the configuration of RAM, FPGA into working state. After power off and FPGA back into a white piece, internal logical relationship, therefore, the FPGA can disappear. The programming without special FPGA, simply use the FPGA programming PROM, general an EPROM programmers. When need to modify the FPGA function, just in a an EPROM can. So, with a FPGA, different programming data, can produce different circuit function. Therefore, the use of FPGA is very flexible.
The FPGA configuration mode.
A variety of configuration mode: FPGA in parallel with the mode of an EPROM for a FPGA: PROM a master-slave mode can support multiple programming FPGA, Serial mode can be adopted FPGA serial PROM programming, Peripheral mode can be FPGA as microprocessors peripherals, by microprocessor for its programming.
How to achieve rapid convergence and reducing consumption of temporal and cost, optimizing the clock management and reduce the FPGA and complexity of PCB concurrent design problems, such as the system has been adopted FPGA design engineers need to consider the key problems. Now, with higher density and FPGA greater capacity, low power consumption and integrated more IP direction development, system design engineer in benefit from these superior performance, had to face because of the performance and capability FPGA unprecedented level of new design challenges.
For example, leading manufacturers recently launched the FPGA Xilinx Virtex - 5 series adopts 65nm process, up to 33 million logic unit, 1,200 I/O and lots of hard IP blocks. Large capacity and the density of the complex cabling become more unpredictable, thus brings more serious timing convergence problem. In addition, the application and integrated according to different Numbers of logic function, DSP, embedded processing and interface module, also let the clock and voltage distribution problem becomes more difficult.
Fortunately, the FPGA manufacturer, supplier is co-operate EDA tools to solve 65nm FPGA design challenges. Not long ago, Synplicity Xilinx announced the formation of large capacity and temporal convergence joint working panel, aimed at maximum design engineer to help to system faster and more efficient way 65nm FPGA device. Design of integrated software vendors Magma Blast tool FPGA can help build up the layout of the optimization, the convergence of the sequence.
Recently the configuration has diversified FPGA!
The FPGA introduced main manufacturers.
1, Altera
2, the Xilinx
3 and Actel
4 and Lattice
One Altera Xilinx and main production general purpose, its main product USES FPGA RAM process. Actel mainly provide nonvolatile FPGA, and products are mainly based on the welding wire technology and FLASH technology.
The FPGA design of attention
Whether you are a logical designers, engineers, hardware engineer or system with all these titles, even if you are in any one kind of high-speed and more complex systems use agreement the FPGA, you will probably need to resolve device configuration, power management, IP integration, signal integrity and other key design problem. However, you don't have to face the challenge, because alone in the leading company in the work of FPGA application engineer every day to solve these problems, and they have put forward some of your design work will become more relaxed design guiding principles and solutions.
The I/O signal
Can provide the most multi-function foot, I/O standard, termination and the difference scheme of FPGA in signal distribution are the most complex design guidelines. Although the FPGA device Altera without design guidelines for its realization are easy, but the spirit of the FPGA design guiding principle is very complicated. But no matter what kind of situation, for I/O pin assignment, there are some need to remember that common steps:
1 the electronic data using a list of all projects, as well as their signal is an important properties, such as I/O standard, voltage, need termination methods and relevant clock.
2 check with the manufacturer for block/regional compatibility.
3. Consider using the second spreadsheets formulate the layout of the FPGA to determine what is common, pipe, which is dedicated to support what difference signal and the global and local clock, which need reference voltage.
4 using the above two spreadsheets information and regional compatibility, distribution rule of maximum extent limitation on foot, signal to the minimum last assignment restricted. For example, you may need to distribution serial bus and clock signal, because they usually only assigned to some specific pin.
5 according to the restricted degree redistribution signal bus. At this stage, may need to carefully weighed and switching output (SSO) and not compatible with the I/O standard design problems, especially when you have many high output or use several different I/O. If your design to local/regional clock, you will probably need to use high-speed bus nearby tube feet, remember this request, to advance the arrangement for the final right foot. If a particular pieces chosen I/O standard reference voltage signal, remember not allocate these pin. Differential signals prior to the distribution throughout the ocl signal. If a FPGA provides piece inside, it also termination rules may apply to other compatibility.
6 in the right place at the distribution of residual signals.
At this stage, consider writing a contains only port of HDL files. Distribution Then through the use of tools or supplier to use a text editor manually create a limit files, for I/O SSO standards and increased the necessary support information. Prepare these basic documents, you can run layout tools to confirm whether wiring overlooked some standards or made a mistake.
This will make you in the initial stage of design and layout engineer working together, common planning of PCB line, redundancy planning, heat and signal integrity. The FPGA tools might help in these aspects, and help you solve these problems, so you must make sure that you understand the toolkit function.
You consult a layout expert late time, you might need to handle some complicated problems and design, and these may be avoided by some preliminary analysis. Once you have achieved satisfactory signal distribution, you must use limit file locking them.
Based on the design of the three main consumption CMOS cut rates: internal (short), leakage of (static) and switch (capacitance). When a gate transient, and short connection between VDD internal power consumption. Leakage power CMOS process is common parasitic effect. But since the power switch is load capacitance, discharge. Switch power consumption together with short circuit is called dynamic power. Following the static and dynamic reduce power consumption of design skills.
Reduces static power
Although the static electricity and dynamic current can be neglected, but compared to battery power handheld devices, it is very important in electricity equipments and when not working. Static electricity of many factors, including is not completely shut off or on the condition of I/O and internal transistors work current, internal connection of resistance, electric drives and three states of pull or pulldown resistor. In the volatile technology, also need some programming information static power. Resistance to fuse is a nonvolatile storage technology, so don't consume static current information.
Introduce below the power of reducing static design method:
? The driver should be fully input voltage level, so all the transistor is completely closed or general guide.
? Because of I/O online, or pulldown resistor in the current consumes must, therefore, avoid the resistance.
? With less driving resistance or bipolar transistors, these devices must maintain a constant current, thus increasing the static electricity.
? According to the clock pin connected to recommend conditions parameter table low level. Impending clock input will greatly increase the static electricity.
? In the design is divided into multiple devices, reduce between the I/O devices.
EX device LP foot use way
The special design Actel eX series of low power "dormancy" mode. In this pin drivers to 800ns high level, low power device into A standby mode, standby current less than 100 mu. At low power mode, all I/O (except the clock at the input), and all three core power. Because of the kernel was stored power trigger the information will be lost, in the work mode into (in pin drivers to match 200ms), the user needs to device initialized again. Likewise, users should close all through the CLKA, CLKB HCLK input and the clock. But the clock is in three states, clock can enter device, thus increasing power, therefore in the low power mode, the clock input must be in logic 0 or logic 1.
Sometimes the user to stop the clock into the device. On this occasion, the user can use and CLKA or CLKA adjacent normal input pin in the design and CLKINT added. So, the clock will pass near the clock will enter, then the normal input device CLKINT through to the device provide clock resources.
Using this input circuit, due to the conventional I/O is three states, so don't worry about the clock into the device. Of course, increase the level of the gate will produce large clock delay 0.6 ns, but luckily it in most low power design is acceptable. Attention should be CLKINT buffers associated with CLKA or CLKB pin grounding.
Also note that CLKINT can only be attachment HCLK clock, don't have to go to the internal network connection HCLK ability, thus HCLK resources can not be regular input. In other words, if use LP pin can use HCLK, When using HCLK should be in external truncation clock signal.
Reducing dynamic power consumption
Dynamic power is the clock work and input is the power switch. To CMOS circuit, dynamic power basically identified. Dynamic power includes several components, mainly is the charging and discharging capacitive load (internal and the I/O) and short-circuited. Most dynamic power is the internal or external capacitor to the device and discharge of consumption. If the device driver multiple I/O load, a large number of dynamic current constitute the main part of the total consumption.
In the design of the drive, the dynamic power is given by the type of computing
P = CL * V 2 x f DD
Type, CL is capacitive load, VDD voltage is, f is switching frequency. Total power is each drive power combined.
Due to the VDD is fixed, reducing internal power will reduce the average logic, reducing switch frequency clock along the logic, reduce the total switch network, especially the high frequency signal attachment of capacitance network connections. For low power design, need to process from system design in each level of prevention measures, the higher level, the better the results.
Identify the FPGA and CPLD
The FPGA and CPLD to identify the main is according to the classification and structure characteristics and working principle. Usually the classification method is:
The product structure to form a logical device called the actions of the Lattice, as ispLSI CPLD Xilinx series, the XC9500 Altera series, the MAX7000S series Lattice and Vantis (original) of Mach series, etc.
By querying method structure form logic device called the actions, such as the FPGA Xilinx SPARTAN Altera series, the FLEX10K or ACEX1K series, etc.
The FPGA applications
The FPGA applications can be divided into three levels: the circuit design, product design, system design in the circuit design 1 FPGA applications
Connecting logic, control logic is the FPGA early role of large area is used. In fact the cornerstone of FPGA in circuit design of difficulty or application of FPGA bigger this requirement developers should have corresponding hardware circuit knowledge and knowledge (software application ability (development tools) this talent shortage, often have always engaged in new technology, new product development of successful product will become the mainstream market based products for product designer used in the near future, the general and special IP design will become a popular profession! Make the circuit design is the premise of must have certain hardware knowledge. In this aspect, dry on learning, of course, rapid introduction is very important, the better the others circuitdevelopment seats are golden bowl.
2 the products design
The relatively mature technology applied to certain areas such as communication, video, information processing, etc. To develop industries and industries can be accepted that the product is mainly the FPGA technology and professional technology, professional customers and also is the interface design of products includes professional tools and products, the former, the latter focus on performance to price sensitive products designed to achieve product functions as the main purpose, FPGA technology is a means of realization, because in this field have interface, control the FPGA, IP, inline function characteristics such as CPU has a simple structure, high degree of curing, comprehensive functions of product design system is applied to the majority of FPGA technology market, has great explosive demand space of technical personnel of product design, and more demanding but now is long established throughout the industry in China is the "start" state, as long as the team, a bright future product design is a professional development direction positioning, is not a simple love can do! Product design domain will foster a large number of enterprises and entrepreneurs, is a recent development opportunities and hot
3 system application
The system is applied in computer technology with traditional FPGA, a computer system as the FPGA edition with Xilinx V - 4, V - 5 series, realize the FPGA embedded CPU POWER PC, and then with various peripheral function, a basic environment, in the LINIX run as the system will support system of standard peripherals and functional interfaces (such as the image interface) for rapid constitute the FPGA large-scale system is very helpful. This "hold" taste very thick system early advantage not obviously, similar to the situation, but if the ARM system can play out slowly and gradually realize the FPGA advantage of some characteristics of system is a development direction. If the system application developer does not have system, the expansion of the development ability, but since meaningless programming is, of course, the device driver development is another kind of situation and system application seemingly high starting point, but don't have deep development ability, will probably become lovers, many people would like to do, but not as what is similar to the above will programming, the hope can help personal development to study the FPGA but very mad at the same ideas first. This is a good profession, have very good personal success opportunity. But also affirmation is a very competitive industry, the key is the speed and depth, of course, market adaptiveness
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