设计一个双优先编码器，不仅能识别出最高优先级，还能在8个请求输入中找出第二高优先级的确认（verilog） 优先编码器只对同时输入的信号中的优先级别最高的一个信号编码？
\u4f7f\u7528Verilog\u8bed\u53e5 \uff0c \u5982\u4f55\u4f7f\u4e00\u4e2a\u53cc\u4f18\u5148\u7f16\u7801\u5668\u80fd\u57288\u4e2a\u8bf7\u6c42\u8f93\u5165\u4e2d\u627e\u51fa\u7b2c\u4e8c\u9ad8\u4f18\u5148\u7ea7\u7684\u786e\u8ba4\u4fe1\u53f7Verilog\u548cVHDL\u7684\u5e02\u573a\u4efd\u989d\u5404\u5360\u4e00\u534a\u3002\u6211\u7528\u53ea\u4f1a\u7528VHDL\u89e3\u51b3\u8fd9\u4e2a\u95ee\u9898\uff1a
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity priority2 is
port(
R: in STD_LOGIC_VECTOR(0 to 7);
A,B: out STD_LOGIC_VECTOR(2 downto 0);
E1,E2: buffer STD_LOGIC
);
end priority2;
architecture priority2_arch of priority2 is
begin
process(R,E1,E2)
begin
A <="000";B <="000";E1 <='0';E2 <='0';
for i in 0 to 7 loop
if R(i)= '1' and E1= '0' then
A <=CONV_STD_LOGIC_VECTOR(i,3);E1 <='1';
elsif R(i)='1'and E2='0' then
B <=CONV_STD_LOGIC_VECTOR(I,3);E2 <='1';
end if;
end loop;
end process;
end priority2_arch;
\u5e0c\u671b\u53ef\u4ee5\u5e2e\u52a9\u5230\u4f60\u3002
\u4f18\u5148\u7f16\u7801\u5668\u5728\u6709\u591a\u4e2a\u8f93\u5165\u4fe1\u53f7\u8981\u6c42\u7f16\u7801\u65f6\uff0c\u4f1a\u9009\u62e9\u8f93\u5165\u7684\u4fe1\u53f7\u4e2d\u7684\u7ea7\u522b\u6700\u9ad8\u7684\u4e00\u4e2a\u4fe1\u53f7\u4f18\u5148\u7f16\u7801\u3002
input [11:0] req,
output reg [3:0] first,
output [3:0] second
);
reg[11:0] reg_req;
wire[11:0] wire_req;
assign wire_req = reg_req;
wire wire_en;
reg reg_en;
assign wire_en = reg_en;
always@(*)
begin
reg_en=0;
first=4'bzzzz;
reg_req=req;
if( req[11] )
begin
reg_req[11]=0;
first=4'b1011;
reg_en=1;
end
else if( req[10] )
begin
reg_req[10]=0;
first=4'b1010;
reg_en=1;
end
else if( req[9] )
begin
reg_req[9]=0;
first=4'b1001;
reg_en=1;
end
else if( req[8] )
begin
reg_req[8]=0;
first=4'b1000;
reg_en=1;
end
else if( req[7] )
begin
reg_req[7]=0;
first=4'b0111;
reg_en=1;
end
else if( req[6] )
begin
reg_req[6]=0;
first=4'b0110;
reg_en=1;
end
else if( req[5] )
begin
reg_req[5]=0;
first=4'b0101;
reg_en=1;
end
else if( req[4] )
begin
reg_req[4]=0;
first=4'b0100;
reg_en=1;
end
else if( req[3] )
begin
reg_req[3]=0;
first=4'b0011;
reg_en=1;
end
else if( req[2] )
begin
reg_req[2]=0;
first=4'b0010;
reg_en=1;
end
else if( req[1] )
begin
reg_req[1]=0;
first=4'b0001;
reg_en=1;
end
else
begin
reg_req[0]=0;
first=4'b0001;
reg_en=0;
end
end
en_code en_code1(
. a(reg_req),
. ena(wire_en),
. code(second)
);
endmodule
怎么金燕华过了四年还出同一个题目！现在又来了
哎，我也想知道答案啊，金燕华大才啊！
楼上的答案太经典了~~
大哥，你老师是金燕华吧？自己做吧...
绛旓細reg_req[1]=0;first=4'b0001;
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