51系列和52系列单片机同时带有AD、spi功能的单片机有哪些？请高手指明型号。
51\u5355\u7247\u673aSPI\u63a5\u53e3\u662f\u4ec0\u4e48\uff1f\u6069\uff0c\u662f\u7684\uff0c51\u5355\u7247\u673a\u6ca1\u6709\u5e26SPI\u63a7\u5236\u5668\u3002\u7ed9\u4f60\u6a21\u62dfSPI\u63a7\u5236nRF24L01\u7a0b\u5e8f\u53c2\u8003\uff0c\u6211\u7684\u8054\u7cfb\u65b9\u5f0f\u770b\u6211\u540d\u5b57
#include
#include
typedef unsigned char uchar;
typedef unsigned char uint;
//****************************************IO\u7aef\u53e3\u5b9a\u4e49***************************************
sbit CSN =P2^0; //SPI \u7247\u9009\u4f7f\u80fd,\u4f4e\u7535\u5e73\u4f7f\u80fd
sbit MOSI =P2^1; //SPI\u4e32\u884c\u8f93\u5165
sbit IRQ =P2^2; //\u4e2d\u65ad.\u4f4e\u7535\u5e73\u4f7f\u80fd
sbit MISO =P2^3; //SPI\u4e32\u884c\u8f93\u51fa
sbit SCK =P2^4; //SPI\u65f6\u949f
sbit CE =P2^5; //\u82af\u7247\u4f7f\u80fd,\u9ad8\u7535\u5e73\u4f7f\u80fd
//***********************************\u6570\u7801\u7ba10-9\u7f16\u7801*******************************************
uchar seg[10]={0xC0,0xCF,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90}; //0~~9\u6bb5\u7801
uchar TxBuf[32]=
{ /*
0x01,0x02,0x03,0x4,0x05,0x06,0x07,0x08,
0x09,0x10,0x11,0x12,0x13,0x14,0x15,0x16,
0x17,0x18,0x19,0x20,0x21,0x22,0x23,0x24,
0x25,0x26,0x27,0x28,0x29,0x30,0x31,0x32,
*/
0x00
}; //
//************************************\u6309\u952e**********************************************
sbit KEY1=P3^6;
sbit KEY2=P3^7;
//***********************************\u6570\u7801\u7ba1\u4f4d\u9009**************************************************
sbit led1=P2^1;
sbit led0=P2^0;
sbit led2=P2^2;
sbit led3=P2^3;
//*********************************************NRF24L01*************************************
#define TX_ADR_WIDTH 5 // 5 uints TX address width
#define RX_ADR_WIDTH 5 // 5 uints RX address width
#define TX_PLOAD_WIDTH 32 // 20 uints TX payload
#define RX_PLOAD_WIDTH 32 // 20 uints TX payload
uint const TX_ADDRESS[TX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}; //\u672c\u5730\u5730\u5740
uint const RX_ADDRESS[RX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}; //\u63a5\u6536\u5730\u5740
//***************************************NRF24L01\u5bc4\u5b58\u5668\u6307\u4ee4*******************************************************
#define READ_REG 0x00 // \u8bfb\u5bc4\u5b58\u5668\u6307\u4ee4
#define WRITE_REG 0x20 // \u5199\u5bc4\u5b58\u5668\u6307\u4ee4
#define RD_RX_PLOAD 0x61 // \u8bfb\u53d6\u63a5\u6536\u6570\u636e\u6307\u4ee4
#define WR_TX_PLOAD 0xA0 // \u5199\u5f85\u53d1\u6570\u636e\u6307\u4ee4
#define FLUSH_TX 0xE1 // \u51b2\u6d17\u53d1\u9001 FIFO\u6307\u4ee4
#define FLUSH_RX 0xE2 // \u51b2\u6d17\u63a5\u6536 FIFO\u6307\u4ee4
#define REUSE_TX_PL 0xE3 // \u5b9a\u4e49\u91cd\u590d\u88c5\u8f7d\u6570\u636e\u6307\u4ee4
#define NOP 0xFF // \u4fdd\u7559
//*************************************SPI(nRF24L01)\u5bc4\u5b58\u5668\u5730\u5740****************************************************
#define CONFIG 0x00 // \u914d\u7f6e\u6536\u53d1\u72b6\u6001\uff0cCRC\u6821\u9a8c\u6a21\u5f0f\u4ee5\u53ca\u6536\u53d1\u72b6\u6001\u54cd\u5e94\u65b9\u5f0f
#define EN_AA 0x01 // \u81ea\u52a8\u5e94\u7b54\u529f\u80fd\u8bbe\u7f6e
#define EN_RXADDR 0x02 // \u53ef\u7528\u4fe1\u9053\u8bbe\u7f6e
#define SETUP_AW 0x03 // \u6536\u53d1\u5730\u5740\u5bbd\u5ea6\u8bbe\u7f6e
#define SETUP_RETR 0x04 // \u81ea\u52a8\u91cd\u53d1\u529f\u80fd\u8bbe\u7f6e
#define RF_CH 0x05 // \u5de5\u4f5c\u9891\u7387\u8bbe\u7f6e
#define RF_SETUP 0x06 // \u53d1\u5c04\u901f\u7387\u3001\u529f\u8017\u529f\u80fd\u8bbe\u7f6e
#define STATUS 0x07 // \u72b6\u6001\u5bc4\u5b58\u5668
#define OBSERVE_TX 0x08 // \u53d1\u9001\u76d1\u6d4b\u529f\u80fd
#define CD 0x09 // \u5730\u5740\u68c0\u6d4b
#define RX_ADDR_P0 0x0A // \u9891\u90530\u63a5\u6536\u6570\u636e\u5730\u5740
#define RX_ADDR_P1 0x0B // \u9891\u90531\u63a5\u6536\u6570\u636e\u5730\u5740
#define RX_ADDR_P2 0x0C // \u9891\u90532\u63a5\u6536\u6570\u636e\u5730\u5740
#define RX_ADDR_P3 0x0D // \u9891\u90533\u63a5\u6536\u6570\u636e\u5730\u5740
#define RX_ADDR_P4 0x0E // \u9891\u90534\u63a5\u6536\u6570\u636e\u5730\u5740
#define RX_ADDR_P5 0x0F // \u9891\u90535\u63a5\u6536\u6570\u636e\u5730\u5740
#define TX_ADDR 0x10 // \u53d1\u9001\u5730\u5740\u5bc4\u5b58\u5668
#define RX_PW_P0 0x11 // \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6
#define RX_PW_P1 0x12 // \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6
#define RX_PW_P2 0x13 // \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6
#define RX_PW_P3 0x14 // \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6
#define RX_PW_P4 0x15 // \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6
#define RX_PW_P5 0x16 // \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6
#define FIFO_STATUS 0x17 // FIFO\u6808\u5165\u6808\u51fa\u72b6\u6001\u5bc4\u5b58\u5668\u8bbe\u7f6e
//**************************************************************************************
void Delay(unsigned int s);
void inerDelay_us(unsigned char n);
void init_NRF24L01(void);
uint SPI_RW(uint uchar);
uchar SPI_Read(uchar reg);
void SetRX_Mode(void);
uint SPI_RW_Reg(uchar reg, uchar value);
uint SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars);
uint SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars);
unsigned char nRF24L01_RxPacket(unsigned char* rx_buf);
void nRF24L01_TxPacket(unsigned char * tx_buf);
//*****************************************\u957f\u5ef6\u65f6*****************************************
void Delay(unsigned int s)
{
unsigned int i;
for(i=0; i<s; i++);
for(i=0; i<s; i++);
}
//******************************************************************************************
uint bdata sta; //\u72b6\u6001\u6807\u5fd7
sbit RX_DR =sta^6;
sbit TX_DS =sta^5;
sbit MAX_RT =sta^4;
/******************************************************************************************
/*\u5ef6\u65f6\u51fd\u6570
/******************************************************************************************/
void inerDelay_us(unsigned char n)
{
for(;n>0;n--)
_nop_();
}
//****************************************************************************************
/*NRF24L01\u521d\u59cb\u5316
//***************************************************************************************/
void init_NRF24L01(void)
{
inerDelay_us(100);
CE=0; // chip enable
CSN=1; // Spi disable
SCK=0; // Spi clock line init high
SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // \u5199\u672c\u5730\u5730\u5740
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); // \u5199\u63a5\u6536\u7aef\u5730\u5740
SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // \u9891\u90530\u81ea\u52a8 ACK\u5e94\u7b54\u5141\u8bb8
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // \u5141\u8bb8\u63a5\u6536\u5730\u5740\u53ea\u6709\u9891\u90530\uff0c\u5982\u679c\u9700\u8981\u591a\u9891\u9053\u53ef\u4ee5\u53c2\u8003Page21
SPI_RW_Reg(WRITE_REG + RF_CH, 0); // \u8bbe\u7f6e\u4fe1\u9053\u5de5\u4f5c\u4e3a2.4GHZ\uff0c\u6536\u53d1\u5fc5\u987b\u4e00\u81f4
SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); //\u8bbe\u7f6e\u63a5\u6536\u6570\u636e\u957f\u5ea6\uff0c\u672c\u6b21\u8bbe\u7f6e\u4e3a32\u5b57\u8282
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); //\u8bbe\u7f6e\u53d1\u5c04\u901f\u7387\u4e3a1MHZ\uff0c\u53d1\u5c04\u529f\u7387\u4e3a\u6700\u5927\u503c0dB
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQ\u6536\u53d1\u5b8c\u6210\u4e2d\u65ad\u54cd\u5e94\uff0c16\u4f4dCRC\uff0c\u4e3b\u53d1\u9001
}
/****************************************************************************************************
/*\u51fd\u6570\uff1auint SPI_RW(uint uchar)
/*\u529f\u80fd\uff1aNRF24L01\u7684SPI\u5199\u65f6\u5e8f
/****************************************************************************************************/
uint SPI_RW(uint uchar)
{
uint bit_ctr;
for(bit_ctr=0;bit_ctr<8;bit_ctr++) // output 8-bit
{
MOSI = (uchar & 0x80); // output 'uchar', MSB to MOSI
uchar = (uchar << 1); // shift next bit into MSB..
SCK = 1; // Set SCK high..
uchar |= MISO; // capture current MISO bit
SCK = 0; // ..then set SCK low again
}
return(uchar); // return read uchar
}
/****************************************************************************************************
/*\u51fd\u6570\uff1auchar SPI_Read(uchar reg)
/*\u529f\u80fd\uff1aNRF24L01\u7684SPI\u65f6\u5e8f
/****************************************************************************************************/
uchar SPI_Read(uchar reg)
{
uchar reg_val;
CSN = 0; // CSN low, initialize SPI communication...
SPI_RW(reg); // Select register to read from..
reg_val = SPI_RW(0); // ..then read registervalue
CSN = 1; // CSN high, terminate SPI communication
return(reg_val); // return register value
}
/****************************************************************************************************/
/*\u529f\u80fd\uff1aNRF24L01\u8bfb\u5199\u5bc4\u5b58\u5668\u51fd\u6570
/****************************************************************************************************/
uint SPI_RW_Reg(uchar reg, uchar value)
{
uint status;
CSN = 0; // CSN low, init SPI transaction
status = SPI_RW(reg); // select register
SPI_RW(value); // ..and write value to it..
CSN = 1; // CSN high again
return(status); // return nRF24L01 status uchar
}
/****************************************************************************************************/
/*\u51fd\u6570\uff1auint SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars)
/*\u529f\u80fd: \u7528\u4e8e\u8bfb\u6570\u636e\uff0creg\uff1a\u4e3a\u5bc4\u5b58\u5668\u5730\u5740\uff0cpBuf\uff1a\u4e3a\u5f85\u8bfb\u51fa\u6570\u636e\u5730\u5740\uff0cuchars\uff1a\u8bfb\u51fa\u6570\u636e\u7684\u4e2a\u6570
/****************************************************************************************************/
uint SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars)
{
uint status,uchar_ctr;
CSN = 0; // Set CSN low, init SPI tranaction
status = SPI_RW(reg); // Select register to write to and read status uchar
for(uchar_ctr=0;uchar_ctr<uchars;uchar_ctr++)
pBuf[uchar_ctr] = SPI_RW(0); //
CSN = 1;
return(status); // return nRF24L01 status uchar
}
/*********************************************************************************************************
/*\u51fd\u6570\uff1auint SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars)
/*\u529f\u80fd: \u7528\u4e8e\u5199\u6570\u636e\uff1a\u4e3a\u5bc4\u5b58\u5668\u5730\u5740\uff0cpBuf\uff1a\u4e3a\u5f85\u5199\u5165\u6570\u636e\u5730\u5740\uff0cuchars\uff1a\u5199\u5165\u6570\u636e\u7684\u4e2a\u6570
/*********************************************************************************************************/
uint SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars)
{
uint status,uchar_ctr;
CSN = 0; //SPI\u4f7f\u80fd
status = SPI_RW(reg);
for(uchar_ctr=0; uchar_ctr<uchars; uchar_ctr++) //
SPI_RW(*pBuf++);
CSN = 1; //\u5173\u95edSPI
return(status); //
}
/****************************************************************************************************/
/*\u51fd\u6570\uff1avoid SetRX_Mode(void)
/*\u529f\u80fd\uff1a\u6570\u636e\u63a5\u6536\u914d\u7f6e
/****************************************************************************************************/
void SetRX_Mode(void)
{
CE=0;
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // IRQ\u6536\u53d1\u5b8c\u6210\u4e2d\u65ad\u54cd\u5e94\uff0c16\u4f4dCRC \uff0c\u4e3b\u63a5\u6536
CE = 1;
inerDelay_us(130);
}
/******************************************************************************************************/
/*\u51fd\u6570\uff1aunsigned char nRF24L01_RxPacket(unsigned char* rx_buf)
/*\u529f\u80fd\uff1a\u6570\u636e\u8bfb\u53d6\u540e\u653e\u5982rx_buf\u63a5\u6536\u7f13\u51b2\u533a\u4e2d
/******************************************************************************************************/
unsigned char nRF24L01_RxPacket(unsigned char* rx_buf)
{
unsigned char revale=0;
sta=SPI_Read(STATUS); // \u8bfb\u53d6\u72b6\u6001\u5bc4\u5b58\u5176\u6765\u5224\u65ad\u6570\u636e\u63a5\u6536\u72b6\u51b5
if(RX_DR) // \u5224\u65ad\u662f\u5426\u63a5\u6536\u5230\u6570\u636e
{
CE = 0; //SPI\u4f7f\u80fd
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer
revale =1; //\u8bfb\u53d6\u6570\u636e\u5b8c\u6210\u6807\u5fd7
}
SPI_RW_Reg(WRITE_REG+STATUS,sta); //\u63a5\u6536\u5230\u6570\u636e\u540eRX_DR,TX_DS,MAX_PT\u90fd\u7f6e\u9ad8\u4e3a1\uff0c\u901a\u8fc7\u51991\u6765\u6e05\u695a\u4e2d\u65ad\u6807\u5fd7
return revale;
}
/***********************************************************************************************************
/*\u51fd\u6570\uff1avoid nRF24L01_TxPacket(unsigned char * tx_buf)
/*\u529f\u80fd\uff1a\u53d1\u9001 tx_buf\u4e2d\u6570\u636e
/**********************************************************************************************************/
void nRF24L01_TxPacket(unsigned char * tx_buf)
{
CE=0; //StandBy I\u6a21\u5f0f
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // \u88c5\u8f7d\u63a5\u6536\u7aef\u5730\u5740
SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // \u88c5\u8f7d\u6570\u636e
// SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQ\u6536\u53d1\u5b8c\u6210\u4e2d\u65ad\u54cd\u5e94\uff0c16\u4f4dCRC\uff0c\u4e3b\u53d1\u9001
CE=1; //\u7f6e\u9ad8CE\uff0c\u6fc0\u53d1\u6570\u636e\u53d1\u9001
inerDelay_us(10);
}
/***********************************************************************************************************
/*\u51fd\u6570\uff1ainit_uart(void)
/*\u529f\u80fd\uff1a\u521d\u59cb\u5316\u4e32\u53e3;\u6ce2\u7279\u73874800bps
/**********************************************************************************************************/
void init_uart(void)
{
SCON = 0x50;
TMOD = 0x20;
TH1 = 0xFA;
TL1 = 0xFA;
PCON = 0x00;
TR1 = 1;
}
//************************************\u901a\u8fc7\u4e32\u53e3\u5c06\u63a5\u6536\u5230\u6570\u636e\u53d1\u9001\u7ed9PC\u7aef**************************************
void R_S_Byte(uchar R_Byte)
{
SBUF = R_Byte;
while( TI == 0 ); //\u67e5\u8be2\u6cd5
TI = 0;
}
//************************************\u5de5\u4f5c\u6307\u793a\u706f**************************************
void power_on(void)
{
P0 = 0xfd;
Delay(6000);
P0 = 0xff;
Delay(6000);
}
//************************************\u4e3b\u51fd\u6570************************************************************
void main(void)
{
uchar i;
uchar temp =0;
init_uart();
init_NRF24L01();
nRF24L01_TxPacket(TxBuf); // Transmit Tx buffer data
Delay(6000);
//CE = 1;
while(1)
{
power_on();
nRF24L01_TxPacket(TxBuf);
SPI_RW_Reg(WRITE_REG+STATUS,0XFF);
Delay(100);
//Delay(6000);
TxBuf[31] = TxBuf[31] + 1;
}
}
可以看看：STK6031，STK6032，STK6033，STK6037，STK60516
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