m序列Verilog程序，多项式为1+X^2+X^3，在线等。。。 已知m序列生成多项式为y＝1+x^2+x^3+x^4+x^8...
m\u5e8f\u5217vhdl\u7a0b\u5e8f\uff0c\u591a\u9879\u5f0ff(x)=1+x^2+x^3+x^4+x^8 \uff0c\u5728\u7ebf\u7b49\u3002\u3002\u5f88\u7b80\u5355\u7684\uff0c\u4f60\u5148\u628a\u5b83\u7535\u8def\u56fe\u753b\u51fa\u6765\uff0c\u7136\u540e\u5c31\u77e5\u9053\u600e\u4e48\u5199\u4e86\u3002
temp=x0&x2&x3&x4&x8
dout8<=dout8&temp
\u5176\u4f59\u7167\u6284\u5c31\u53ef\u4ee5\u4e86\u3002
\u4f60\u53ef\u4ee5\u5b66\u4e60\u4e00\u4e0b\u591a\u9879\u5f0f\u548c\u79fb\u4f4d\u5bc4\u5b58\u5668\u7684\u5173\u7cfb\u5c31\u77e5\u9053\u4e86
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PRSG is
port (reset,clk:in std_logic;
sel:in std_logic_vector(1 downto 0);
dout:out std_logic_vector(7 downto 0));
end PRSG;
architecture behavioral of PRSG is
signal ddout:std_logic_vector(7 downto 0);
signal temp:std_logic;
begin
process(sel)
begin
if reset='1' then
ddout
module m_sequences(clk,signal);
input clk;
output signal;
reg signal;
reg c1,c2,c3;
reg c0=1;
always@(posedge clk)
begin
c3<=c2;
c2<=c1;
c1<=c0;
c0<=c3 + c2 ;
signal<=c3;
end
endmodule
具体细节可以看一些关于通原方面的知识，其实就是几个反馈移位寄存器，很简单
就是一个简单的移位寄存器，用于产生伪随机系列。
绛旓細begin //5绾M搴忓垪缂栫爜 M_buf[4] <= M_buf[0]^M_buf[3];M_buf[0] <= M_buf[1];M_buf[1] <= M_buf[2];M_buf[2] <= M_buf[3];M_buf[3] <= M_buf[4];end end
绛旓細module m_sequences(clk,signal);input clk;output signal;reg signal;reg c1,c2,c3;reg c0=1;always@(posedge clk)begin c3<=c2;c2<=c1;c1<=c0;c0<=c3 + c2 ;signal<=c3;end endmodule 鍏蜂綋缁嗚妭鍙互鐪嬩竴浜涘叧浜庨氬師鏂归潰鐨勭煡璇嗭紝鍏跺疄灏辨槸鍑犱釜鍙嶉绉讳綅瀵勫瓨鍣紝寰堢畝鍗 ...
绛旓細鎴m搴忓垪浠ｇ爜璧嬪间笅鏉ユ槸锛屽彂鐜皐ire鍜寈涓棿娌℃湁绌烘牸锛岃繖鍙兘鏄鑷翠綘娌℃湁杈撳嚭鐨勫師鍥狅紝涓汉寤鸿浣犵殑浠ｇ爜杩欐牱鍐欙細module prbs(clk,rst,m_out);input clk,rst;output m_out;reg[7:0]reg_buf;reg x;always@(posedge clk or posedge rst)if(!rst)begin reg_buf[7:0]<= 8'b1000_0000;x <= 1...
绛旓細鎴m搴忓垪浠ｇ爜璧嬪间笅鏉ユ槸锛屽彂鐜皐ire鍜寈涓棿娌℃湁绌烘牸锛岃繖鍙兘鏄鑷翠綘娌℃湁杈撳嚭鐨勫師鍥狅紝涓汉寤鸿浣犵殑浠ｇ爜杩欐牱鍐欙細module prbs(clk,rst,m_out);input clk,rst;output m_out;reg[7:0] reg_buf;reg x;always@(posedge clk or posedge rst)if(!rst)begin reg_buf[7:0] <= 8'b1000_0000;x...
绛旓細閲囩敤M搴忓垪锛鍙互寰楀埌浼殢鏈烘暟銆 濡傛灉鏁板ぇ浜50锛屽彲浠ュ皢鐢熸垚鏁板噺鍘50鍗冲彲銆傚鏋滅浜屾寰楀埌鐨勬暟瀛楃瓑浜庣涓娆★紝鍐嶄粠鏂扮敓鎴愪竴娆″嵆鍙紝鎴栬呬繚闄╄捣瑙佸彲浠ョ敤涓や釜浼殢鏈虹瀛愭潵鐢熸垚M搴忓垪浼殢鏈烘暟銆2锛岄噰鐢ㄤ袱涓笉鍚岄鐜囩殑淇″彿婧愬紓鎴栵紝鐒跺悗瀵瑰紓鎴栦俊鍙蜂娇鐢ㄧ涓変釜鏃堕挓淇″彿閲囨牱锛屼篃鍙緱鍒伴殢鏈烘暟銆傚悗缁鐞嗗彲涓婇潰涓鏍枫
绛旓細浠ｇ爜鐨勯煹寰嬶細Verilog HDL鐨勭紪鑸 鍦╒erilog HDL鐨勮垶鍙颁笂锛宮搴忓垪鐨鐢熸垚鍣ㄤ互涓ヨ皑鐨勯昏緫瑙勫垯婕旂粠瀹冪殑鑸炶箞銆備竴娈电畝娲佺殑妯″潡浠ｇ爜鎻ず浜嗙Щ浣嶅瘎瀛樺櫒鐨勫姩鎬佹洿鏂板拰鍙嶉鏈哄埗锛屾瘡涓椂閽熷懆鏈熼兘鏄竴娆″崕涓界殑搴忓垪杞崲銆傚綋浣犵湅鍒颁豢鐪熸尝褰腑閭31涓懆鏈熺殑鏃犵紳琛旀帴锛屼豢浣涜兘鍚m搴忓垪鐨勪綆璇傛帰绱㈢殑缁堢偣锛氭洿澶氱煡璇嗕笌璧勬簮 鎯宠浜嗚В...
绛旓細鍣 杩欎釜鍙笉涓瀹氬晩锛屽畠浼殢鏈搴忓垪鍟婏紝澶у摜 浣犲掓槸鎶婃垜鐨勫洖绛旈兘缁欓噰绾充簡鍚
绛旓細.clk(clk_M));//浜х敓M搴忓垪 mydds dds_ask(.gclock(clk),.clr(clr),.fcw(fcw),.pcw(angle),.outputwave(dpsk_zaibo)); //姝ｅ鸡鍙戠敓妯″潡锛屼骇鐢熻浇娉 always@(posedge clk)begin if(EN!=0)begin if(M==a)dpsk_output<=~dpsk_zaibo;//褰撳墠鍚庣爜鍏冪浉鍚屾椂杈撳嚭娉㈠舰鐩镐綅涓180 else begin dpsk...
绛旓細绗1绔 缁1锛1 FPGA姒傝堪1锛1锛1 FPGA鍙戝睍鐨勭畝瑕佸洖椤1锛1锛2 FPGA涓嶢SIC1锛2 鍙紪绋嬮昏緫鍣ㄤ欢鐨勫熀鏈蹇1锛3 绠鍗曞彲缂栫▼鍣ㄤ欢(sPLD)鐨勭粨鏋1锛4 楂樺瘑搴﹀彲缂栫▼閫昏緫鍣ㄤ欢1锛4锛1 澶嶆潅鍙紪绋嬮昏緫鍣ㄤ欢CPLD1锛4锛2 鐜板満鍙紪绋嬮棬闃靛垪FPGA1锛4锛3 CPLD鍜孎PGA鐨勫尯鍒1锛4锛4 FPGA/CPLD鍘傚绠浠1锛5鍩轰簬...
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