关于verilog实现的串并转换功能 用状态机如何实现并串转换verilog

verilog\u5e76\u4e32\u8f6c\u6362\u548c\u4e32\u5e76\u8f6c\u6362\u95ee\u9898

always@(posedge pclk,posedge reset)
begin
if(reset) begin
p<=0;
end
else begin
p<=din;
end
end
always@(posedge sclk,posedge reset)
begin
if(reset) ser_d<=0;
else
begin
if(x!=7) begin
{p,ser_d}<={1'b0,p};
end
else ser_d<=p[0];
end
end
\u8fd9\u91cc\u7f16\u8bd1\u5668\u6ca1\u62a5\u9519\u5417\uff1fp\u6709\u4e24\u79cd\u9a71\u52a8
\u8fd8\u6709\u9694\u79bb\u4e0d\u540c\u65f6\u949f\u57df\u6700\u597d\u8981\u7528fifo\u7684\uff0c\u6211\u5c31\u5728\u4f60\u7684\u57fa\u7840\u4e0a\u6539\u4e86

`timescale 1ns/1ns
module p2s2p(reset,pclk,sclk,din,dout);
input reset,pclk,sclk;
input [7:0]din;
output reg[7:0]dout;
reg ser_d;
reg [7:0]d,p,q;
reg [2:0]x;
reg s;
always@(posedge sclk,posedge reset)
begin
if(reset) begin
p<=0;
end
else if(x==1)begin
p<=din;
end
else begin
p<={1'b0,p[7:1]};
end
end
always@(posedge sclk,posedge reset)
begin
if(reset) ser_d<=0;
else
begin
ser_d<=p[0];
end
end
always@(posedge sclk,posedge reset)
begin
if(reset) x<=3'b0;
else begin
x<=x+1;
end
end
always@(posedge sclk,posedge reset)
begin
if(reset) s<=0;
else begin
if(x==2) s<=1;
else s<=0;
end
end
always@(posedge sclk,posedge reset)
begin
if(reset) d<=8'b0;
else begin
d<={ser_d,d[7:1]};
end
end
always@(posedge sclk,posedge reset)
begin
if(reset) q<=8'b0;
else begin
if(s) q<=d;
end
end
always@(posedge pclk,posedge reset)
begin
if(reset) dout<=8'b0;
else begin
dout<=q;
end
end
endmodule

\u6211\u7ed9\u4f60\u8be5\u4e86\u4e24\u5904\uff0c\u4e00\u662f\u4f60\u7684\u5206\u9891\u90e8\u5206\uff0c\u7531\u4e8e\u4f60\u91c7\u7528\u7684\u4e0d\u662f50%\u7684\u5360\u7a7a\u6bd4\uff0c\u800c\u53c8\u8981\u628a\u5f97\u5230\u7684\u9891\u7387\u7528\u505a\u65f6\u949f\uff0c\u5f88\u53ef\u80fd\u9020\u6210\u540e\u9762\u6570\u636e\u65e0\u6cd5\u6ee1\u8db3\u5efa\u7acb\u548c\u4fdd\u6301\u65f6\u95f4\u5bfc\u81f4\u9519\u8bef\uff0c\u8be5\u540e\u7684\u4ee3\u7801\u5982\u4e0b\uff1a
always@(posedge clk)
begin
if (counter_224=='d112) // 224\u5206\u9891\u7684\u8ba1\u6570\u5668,64k
begin
clk_224<=~clk_224;
counter_224<=8'b0;
end
else
counter_224<=counter_224+8'b1;

end

always@(posedge clk)
begin
if (counter_128=='d64) // 128\u5206\u9891\u7684\u8ba1\u6570\u5668,112k
begin
clk_128<=~clk_128;
counter_128<=0;
end
else
counter_128<=counter_128+7'b1;

end
\u8fd8\u6709\u5c31\u662f\u4f60\u7684\u5e76\u8f6c\u4e32\u7684\u90e8\u5206\uff0c\u6211\u6ca1\u6709\u7528\u79fb\u4f4d\u5bc4\u5b58\u5668\u7684\u65b9\u5f0f\u800c\u662f\u91c7\u7528\u72b6\u6001\u673a\u6765\u5b9e\u73b0\u7684\uff0c\u4f60\u7684\u4ee3\u7801\u7684\u4e00\u4e2a\u9519\u8bef\u5c31\u662fhanming_encode\u662f7\u4f4d\u7684\u4e0d\u662f6\u4f4d\uff0c\u8fd8\u6709\u4e2a\u4eba\u6bd4\u8f83\u559c\u6b22\u72b6\u6001\u673a\uff0c\u53ef\u80fd\u770b\u4e0a\u53bb\u5b83\u5f88\u7e41\u7410\uff0c\u5176\u5b9e\u8fd9\u4e2d\u601d\u60f3\u5e94\u7528\u5e7f\u6cdb\uff0c\u79fb\u4f4d\u5bc4\u5b58\u5668\u867d\u7136\u4e0d\u7e41\u4f46\u662f\u8001\u5bb9\u6613\u51fa\u9519\uff08\u6211\u6307\u5728\u4e00\u4e9b\u590d\u6742\u7684\u4ee3\u7801\u91cc\uff09\uff0c\u72b6\u6001\u673a\u4ece\u89c6\u89c9\u4e0a\u6765\u8bf4\u6bd4\u8f83\u7e41\u7410\uff0c\u53ef\u662f\u5f88\u5bb9\u6613\u7406\u89e3\u3002\u4ee3\u7801\u5982\u4e0b\uff1a
reg [7:0] state;
always@(posedge clk_128) //\u5e76\u884c\u8f93\u5165,\u4e32\u884c\u8f93\u51fa
begin
case(state)

state1:begin hanming_out<=output_temp[0]; state<=state2; end
state2:begin hanming_out<=output_temp[1]; state<=state3; end
state3:begin hanming_out<=output_temp[2]; state<=state4; end
state4:begin hanming_out<=output_temp[3]; state<=state5; end
state5:begin hanming_out<=output_temp[4]; state<=state6; end
state6:begin hanming_out<=output_temp[5]; state<=state7; end
state7:begin hanming_out<=output_temp[6]; state<=state1; end

default : state<=state1;
endcase
end
\u8fd8\u6709\u4e00\u5904\u5c31\u662f\u7528\u8fde\u7eed\u8d4b\u503c\u7ed9output_temp\u8d4b\u503c\u5982\u4e0b\uff1a
assign output_temp=hanming_encode;
\u5f53\u7136output_temp\u7684\u5b9a\u4e49\u8981\u8be5\u573aWIRE\u578b
PS\uff1a\u6bcf\u6b21\u82b1\u65f6\u95f4\u8ba4\u771f\u5199\u56de\u590d\uff0c\u53ef\u662f\u5c31\u6709\u4e9b\u4eba\u559c\u6b22\u5173\u95ed\u95ee\u9898\uff0c\u6211\u5f88\u90c1\u95f7\uff0c\u4e0d\u77e5\u9053\u8fd8\u80fd\u575a\u6301\u591a\u4e45\u3002

串并转换很简单，就是移位寄存器，后面最好跟一个锁存器，实现你所要求的功能需要四位移位寄存器和四位锁存器，锁存器的作用就是保持并行数据在移位时不发生变化：
module shift(nreset,clk,en,in,out);

input nreset,clk,en,in;
output [3:0] out;

reg [1:0] count;//移位计数，控制并行数据更新，这里是4bit并行数据
reg [3:0] data;
reg [3:0] out;

/* 移位计数，用于并行数据输出，也可以外加一个脉冲控制数据边界，这里移位4bit就并行输出一次*/
always@(posedge clk or negedge nreset)
begin
if(~nreset)
count <= 2'b00;
else if(en)
count <= count + 2'b01;
end
//移位
always@(posedge clk or negedge nreset)
begin
if(~nreset)
data <= 4'b0000;
eale if(en)
data <= {data[2:0],in};
end
//并行输出
always@(posedge clk or negedge nreset)
begin
if(~nreset)
out <= 4'b0000;
else if(en && (count==2'b11))
out <= data;
end
endmodule

我编译、仿真过了，没有问题，你原有的out<={out,in}应该写成像这样data <= {data[2:0],in};这就是一个移位寄存器！

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